//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================


#ifndef WATERTEK_DM9000_DRIVER_H
#define WATERTEK_DM9000_DRIVER_H

#include "SMA_types.h"
#include "net_net.h"

void Dm_Init(void);
void Dm_FastReset( void );
void Dm_Close( void );
void Dm_WriteNodeID( void );
void Dm_Query( void );
UNS_8  *Dm_RcveFrame( void );
void Dm_SendFrame( UNS_8  *outbuf, UNS_16 len );
void ETH_Rcve( UNS_8  *inbuf );
void ETH_Send( UNS_8 *outbuf, UNS_8 *hwaddr, UNS_16 ptype, UNS_16 len );

/******** registers location definition ********/
#define DR_NET_CONTROL      0x00		// network control
#define DR_NET_STATUS       0x01		// network status
#define DR_TX_CONTROL       0x02		// TX control
#define DR_TX_STATUS1		0x03		// TX status 1
#define DR_TX_STATUS2		0x04		// TX status 2
#define DR_RX_CONTROL		0x05		// RX control
#define DR_RX_STATUS		0x06		// RX status
#define DR_RX_OVFCNT        0x07		// RX overflow counter
#define DR_BP_THRES         0x08		// back pressure threshold
#define DR_FC_THRES			0x09		// flow control threshold
#define DR_RX_FLOWCTRL		0x0a		// RX flow control
#define DR_EPPHY_CTRL		0x0b		// EEPROM & PHY control
#define DR_EPPHY_ADDR		0x0c		// EEPROM & PHY address
#define DR_EPPHY_DATALO		0x0d		// EEPROM & PHY data low
#define DR_EPPHY_DATAHI		0x0e		// EEPROM & PHY data high
#define DR_WAKEUP_CTRL		0x0f		// wakeup control
#define DR_PHY_ADDR0		0x10		// 10-15 : physical address registers
#define DR_PHY_ADDR1		0x11		// 10-15 : physical address registers
#define DR_PHY_ADDR2		0x12		// 10-15 : physical address registers
#define DR_PHY_ADDR3		0x13		// 10-15 : physical address registers
#define DR_PHY_ADDR4		0x14		// 10-15 : physical address registers
#define DR_PHY_ADDR5		0x15		// 10-15 : physical address registers
#define DR_MULTICAST0		0x16		// 16-1d : multicast registers
#define DR_MULTICAST1		0x17		// 16-1d : multicast registers
#define DR_MULTICAST2		0x18		// 16-1d : multicast registers
#define DR_MULTICAST3		0x19		// 16-1d : multicast registers
#define DR_MULTICAST4		0x1a		// 16-1d : multicast registers
#define DR_MULTICAST5		0x1b		// 16-1d : multicast registers
#define DR_MULTICAST6		0x1c		// 16-1d : multicast registers
#define DR_MULTICAST7		0x1d		// 16-1d : multicast registers
#define DR_GP_CONTROL		0x1e		// general purpose control
#define DR_GP_REGISTER		0x1f		// general purpose register
#define DR_TXRDPTR_LO		0x22		// TX SRAM read pointer low
#define DR_TXRDPTR_HI		0x23		// TX SRAM read pointer high
#define DR_TXWRPTR_LO		0x24		// TX SRAM write pointer low
#define DR_TXWRPTR_HI		0x25		// TX SRAM write pointer high
#define DR_VENDOR_ID_LO		0x28		// vendor ID low
#define DR_VENDOR_ID_HI		0x29		// vendor ID high
#define DR_PRODUCT_ID_LO	0x2a		// product ID low
#define DR_PRODOCU_ID_HI	0x2b		// product ID high
#define DR_CHIP_REVISION	0x2c		// chip revision
#define DR_SPECMODE_CTRL	0x2f		// special mode control

#define DR_READ_WO_INC		0xf0		// memory data read without addr inc
#define DR_READ_INC			0xf2		// memory data read with addr inc
#define DR_READ_ADDR_LO		0xf4		// memory data read address low
#define DR_READ_ADDR_HI		0xf5		// memory data read address high
#define DR_WRITE_WO_INC		0xf6		// memory data write without addr inc
#define DR_WRITE_INC		0xf8		// memory data write with addr inc
#define DR_WRITE_ADDR_LO	0xfa		// memory data write address low
#define DR_WRITE_ADDR_HI	0xfb		// memory data write address high

#define DR_TXPKT_LEN_LO		0xfc		// TX packet length low
#define DR_TXPKT_LEN_HI		0xfd		// TX packet length high
#define DR_INTR_STATUS		0xfe		// interrupt status
#define DR_INTR_MASK		0xff		// interrupt mask

// interrupt
#define DM9000_TX_INT       _BIT(1)
#define DM9000_RX_INT       _BIT(0)

#endif /* WATERTEK_DM9000_DRIVER_H */
